发明名称 PERFORMANCE EVALUATION METHOD AND DEVICE THEREOF FOR A PARALLEL COMPUTER
摘要 The method and device are applied to a parallel computer which carries out parallel processing by transmitting and receiving messages among a plurality of processors. In a memorizing step (50), various pieces of information are memorized such as an execution starting time, standby starting time for waiting for reception of the message, message number on reception of the message, processor number of the processor, the message and time when the message is received, message number on transmitting the message and message execution ending time. In a step of obtaining the maximum delay path, a last ending processor is identified in which execution was last ended, and the standby starting time for waiting reception of the message in the last ending processor, the message number of the last ending processor, the transmitting processor number and the message transmitting processor corresponding to the transmitting processor number are all searched for among the memorized information. These searches are repeated from the last ending processor to a starting processor where execution of the parallel processing was started. Thus, the maximum delay path can be obtained, allowing recognition of where increased data transmission speed is needed. <IMAGE>
申请公布号 EP0548909(A3) 申请公布日期 1993.09.08
申请号 EP19920121792 申请日期 1992.12.22
申请人 FUJITSU LIMITED 发明人 HORIE, TAKESHI
分类号 G06F9/38;G06F11/34;G06F15/16;G06F15/177;(IPC1-7):G06F11/34 主分类号 G06F9/38
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