| 发明名称 |
Process for planarizing an integrated circuit device. |
| 摘要 |
<p>A thick planarization layer of silicon dioxide that is heat resistant is provided by coating a polysilazane layer over a substrate having steps and firing the polysilazane layer in an oxygen-containing atmosphere to convert the polysilazane to silicon dioxide. The temperature of this conversion may be as low as 400 to 450 DEG C while a higher firing or curing temperature is preferable to obtain a more desified oxide layer. <IMAGE></p> |
| 申请公布号 |
EP0559394(A2) |
申请公布日期 |
1993.09.08 |
| 申请号 |
EP19930301479 |
申请日期 |
1993.02.26 |
| 申请人 |
FUJITSU AUTOMATION LIMITED;KYUSHU FUJITSU ELECTRONICS LIMITED |
发明人 |
SHIN, DAITEI;HARADA, HIDEKI |
| 分类号 |
H01L21/3205;C08G77/62;C08G77/48;H01L21/3105;H01L21/316;H01L21/768;H01L21/822;H01L27/04;(IPC1-7):H01L21/316;H01L21/310 |
主分类号 |
H01L21/3205 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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