APPARATUS AND METHOD FOR TRANSMITTING AND RECEIVING MESSAGE

摘要

The unit utilizes AMD's high speed transmission chip device (TAXI chip) for implementing 100 Mbps class high speed message transfer. And as it employs multi FIFO memory devices, a transmit and receive buffer size is enlarged and a receiving procedure is much simplified. The unit comprises: a processor (100) to control all the transmission procedure; Rx and Tx FIFO memory units (130a,130b) for storing messages and control bits; control units (120a,120b) to distribute message blocks into the FIFO memory units in order; and control bit storage units (110a,110b) to transfer only control bits between the both side processors.