| 摘要 |
PURPOSE: To reduce a convergence time by updating in parallel each product with preceding data as to N-set of coefficients, to bring about complex coefficients whose N-set of coefficients are updated for selective input to an equalizer filter. CONSTITUTION: A multiplier means may be made up of a plurality of programmable logic array(PLA) multiplier stages, corresponding to a plurality of delay stages in a delay section 94. Each delay stage and PLA multiplier stage corresponds to an accumulator and to any of gain adjustment stages 102a-102n to provide a parallel processing path. Each parallel processing path 120 causes a distributed VLSI slice in the manufacture of an integrated circuit. Since a coefficient update calculation circuit updates all N-set of coefficients, in parallel for each filter clock cycle in place of updating one coefficient for one cycle, then no detrimental adverse effect is received on a convergence time of an equalizer, due to the actual execution of the LMS algorithm. |
