| 摘要 |
<p>PURPOSE:To easily output the digital data in the RAM again by storing the input of digital data as a FIFO buffer and outputting the data through RAM in synchronism with a read pulse. CONSTITUTION:The input buffer is provided with 110, dual port RAM 120, write address counter 150, read address counter 160, and control section 130. The reading to the dual port RAM 120 is controlled by a control section 130 based on a collision signal S, outputted through an idle cell insertion circuit 140. In short, the section 130 inputs the collision signal S to detect the state holding the digital data in the FIFO 110. If there is no collision signal S and the FIFO 110 is occupied, the digital data is outputted from the FIFO 110 according to the read pulse. The read pulse is outputted to the write address counter 150 as a counting pulse.</p> |
