| 摘要 |
<p>PURPOSE:To eliminate clock skew adjusting error caused by delay time difference at output buffer gates of the clock skew adjusting circuit. CONSTITUTION:This circuit is provided with delay circuits D111 and D121 to vary the delay time of a clock signal CLK corresponding to control signals S111 and S121 inputted from external control terminals, and selecting circuits SL111 and SL121 to select the inputs and outputs of output buffer gates 0111 and 0121 concerning observing signals for the clock adjustment of a clock distribution circuit composed of plural gates. Further by recognizing the delay time at the output buffer gates SL111 and SL121, delay time difference between both of them is turned to zero.</p> |
