发明名称 PACKET SWITCHING SYSTEM
摘要 <p>PURPOSE:To miniaturize a device and to increase the processing speed by decomposing a variable length packet into small packets so as to apply ATM switching to them and restoring the packets at the output side of a switching section. CONSTITUTION:A buffer 30 is provided on every plural communication lines, a decomposing section 40 receives the output of each buffer 30 and passes through fixed length packet data as it is and decomposes variable length packet data into plural small packets in the unit of small length packets. The switching section 50 receives the output of the decomposing section 40 to apply bus switching processing. A composition section 60 receives the output of the switching section 50 and passes through fixed length packet data as it is and composes a small packet into one variable length packet and the buffer 30 holds tentatively the output of the assembling section 60. The system processes both the fixed length packet and the variable length packet in such a manner and the device is miniaturized and the processing speed is increased.</p>
申请公布号 JPH05227211(A) 申请公布日期 1993.09.03
申请号 JP19920029228 申请日期 1992.02.17
申请人 FUJITSU LTD 发明人 TOMINAGA SUSUMU
分类号 H04L12/56 主分类号 H04L12/56
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