| 摘要 |
PURPOSE:To provide the pi/4 shift QPSK signal demodulation circuit of the delay detection system with a small size and less power consumption. CONSTITUTION:A received signal is branched into a delay detection processing system and a timing synchronization processing system. That is, an IF signal after band limit by a band pass filter 8 is decomposed into I, Q signals by an orthogonal detector 12 including a multiplier 11, converted into a digital signal and identified by a delay detection circuit 25. The other IF signal is given to a frequency detector 28 or the like, in which a symbol timing signal is extracted. The signal is shaped into a pulse and inputted to a delay detection circuit 25 via a DPLL 34. The calculation required for the processing of the delay detection circuit 25 is implemented by using a ROM storing the built-in calculation rules. |
