| 摘要 |
PURPOSE:To reduce the power consumption of a shift registor connected in cascade to a switched inverted by providing a circuit talking AND between the inverted output of each conventional bit and an output signal as each bit. CONSTITUTION:The switched inverter constituting data transfer part 1 is a circuit directly connected to p-MOSFETs Q1, Q2 and n-MOSFETs Q3, Q4. An NAND circuits taking the AND between conventional inverted outputs of respective bits A1, A2,... and conventional output signals of respective bits V1, V2,... are provided and the output signals are defined as phi1, phi2,.... Since one bit shift registor is composed of substantially one switched inverter, the number of MOSFETs is reduced from four to two. Since the frequensies of the clock pulses are reduced by a half, the power consumption is reduced to a quarter of the conventional consumption. |
