BiCMOS LOGIC CIRCUIT

摘要

An improved BiCMOS logic circuit (70) utilizes an emitter-coupled pair of bipolar transistors (21, 22) for differentially comparing an input signal (Vin) with a logic reference level (VBIAS). Each of the bipolar transistors are resistively loaded by a network of p-channel metal-oxide-semiconductor (PMOS) transistors (26, 27) coupled in parallel. At least one of the parallel combination of transistors has its gate coupled to a control signal (VREF2) providing a variable load resistance. The control signal is preferably provided by a feedback network (52, 53) which maintains a constant voltage swing across the network over temperature.