| 摘要 |
<p>n-parallel bits of data are input to a parallel in - parallel out shift register made of n+m n:1 parallel multiplexers and n-parallel bits of either pure data or combined stuff and data bits are output where, for cycles in which stuff bits are inserted, the non-outputted data bits are recirculated for output on a subsequent cycle followed by newly incoming data bits; such is shown used to advantage in a bit stuffing technique where a synchronous payload envelope pattern may be started at a selected location in a synchronous transport signal frame by monitoring a frame starting signal and providing a pattern starting signal at a selected point after the occurrence of the frame starting signal. <IMAGE></p> |
