发明名称 |
Data processor microsequencer having multiple microaddress sources and next microaddress source selection |
摘要 |
A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an instruction decode unit implemented with a plurality of PLAs and also has a microcoded ROM for providing the next microaddress. The instruction decode unit outputs a next microaddress, a next-PLA field, and a ROM-or-PLA control bit. The control bit functions to minimize power in the data processor. The next-PLA field is latched and used to select a single decode unit when the next instruction decode is needed to activate a predetermined decode unit. Early macroinstruction branching can be performed in the data processor thereby improving performance.
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申请公布号 |
US5241637(A) |
申请公布日期 |
1993.08.31 |
申请号 |
US19930015388 |
申请日期 |
1993.02.08 |
申请人 |
MOTOROLA, INC. |
发明人 |
SKRUHAK, ROBERT J.;NASH, JAMES C.;EIFERT, JAMES B. |
分类号 |
G06F9/26 |
主分类号 |
G06F9/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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