| 摘要 |
PURPOSE:To realize high integration density by utilizing non-selected word lines between storage cells provided adjacently in such a direction as connecting the one and the other source drains of transistors, although a folded bit line configuration may be formed. CONSTITUTION:The word lines WL0, WL2 and word lines WL1, WL3 of different layers are alternately extended between storage cells in such a direction as connecting the one 13 and the other 16 of the source drain of a transistor 11 and branching portions 26, 27 are also provided in both sides of the word lines. The branching portion 27 is extended to a storage cell of the next column passing through storage cells provided adjacent to the word lines. Moreover, bit lines BL0 to BL4 are extended in such a direction as orthogonally crossing the word lines. On the occasion of reading stored data from the storage cells, stored data are outputted only to every other bit line to form the folded bit line configuration. |
