| 摘要 |
The device comprises a network of memory cells arranged in a matrix having NAND cells, and formed by a plurality of memory cells connected in series, each of which consists of the superposition of a charge storage layer and a control gate on a semiconductor substrate, and allows electrical erasure by the mutual exchanging of a charge between the charge storage layer and the substrate, a data latch circuit (LT), a high-voltage supply circuit (HV), a current source circuit (CS), a program checking circuit (PC), and a program status detection circuit (PS). <IMAGE>
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