| 摘要 |
PURPOSE:To make it possible to change data length properly by providing the 1st data selecting ciricuit receiving even data and odd data and the 2nd data selecting circuit receiving odd data and zero data. CONSTITUTION:To data selecting circuit 1, binary four-bit even data ED binary four-bit odd data, for example, are input and either data ED or OD are output depending upon selective signal S1. To data selecting circuit 2, data OD and zero data ZD whose four bits are all zero are input and either data OD or ZD are output depending upon selective signal S2. When signals S1 and S2 are both zero, output P from circuit 1 are data ED, and output Q from circuit 2 data OD, so that an eight- -bit binary signal will be output on the whole. Output Q of signal S2 of ''1'' is data ZD and when signal S1 is alternated between ''0'' and ''1'' at this time, data ED and OD are alternately output from output P, so that since output Q is zero, a four- bit binary signal will be sent out. |
