| 摘要 |
PURPOSE:To obtain a decoding circuit capable of taking block synchronization without any adjustment, by using a J-K flip-flop in a frequency division circuit, and inputting a step out detecting signal to the J and the K terminals of the J-K flip-flop. CONSTITUTION:The negative phase output f0CLKi of the J-K flip-flop 16 is phase-compared with a block detecting signal (d) at a phase discrepancy detec tion circuit 10, and a phase discrepancy detecting signal (j) set at 'H' when the phases are discrepant, can be obtained. The content of a phase discrepancy counter 13 is increased by one, at every setting of the phase discrepancy detecting signal at 'H' and a step out signal (n) is set at 'H' when the content detected at a phase discrepancy number detection circuit 14 arrives at a constant number. The timing of the step out signal (n) is rearranged by a 2f0 CLK at a step out detection circuit 15, and a step out detecting signal 0 can be obtained. When the step out detecting signal 0 is set at 'H', the J terminal and the K terminal of the J-K flip-flop 16 are set at 'H's, and the toggle operation of the J-K flip-flop 16 is stopped, and the phase of the f0CLK is shifted by (pi). |
