| 摘要 |
PURPOSE: To provide a multiplier and multiplying method for reducing hardware. CONSTITUTION: In order to multiply an N bit number X (t) by an M bit number C, the number of N bits is divided into bit groups X1 (t), X0 (t) by a register 20, and each bit group generates a value having ((N/K)+M) bits by LUTs 30, 25. A first value in the highest priority order is shifted to an upper weight bit position by each N/K bit by the value of the output of the adjacent LUT. Those values of the LUT are added for preparing a partial product. The process for shifting and adding for obtaining ((2N/K)+M) bits is repeated for the remaining bit groups of the X (t) in each sequence of the priority order. The result of many K/2 addition is transmitted to an adder tree until a single result is obtained, and this single result can be the product of (N+M) bits of the C and the X (t). |
