| 摘要 |
PURPOSE:To enable word access at all times by controlling a memory address count-up quantity to a half as large as that in a case of information saving operation regarding the word access. CONSTITUTION:With the byte area status signal/B3 CY signal outputted from an emulation processor 1, the permit signal/ENABLE of an STM address counter 64 is negated with a counter control circuit 63 to a high level in the 1st bus cycle between two bus cycles to a byte area, and an address STMA is allowed to be counted in the 2nd bus cycle. At this time, a select signal for a memory is generated by a/CS generating circuit 62 which inputs the byte area status signal/B3CY, a word access status signal/WORD, a stack memory control signal STM, and an address A0. In the 1st cycle, the select signal/HCS is asserted to a low level and in the 2nd cycle, the selected signal/LCS is asserted to a low level. |
