| 摘要 |
PURPOSE:To simplify the insurance of recovery time of an input/output instruction and to eliminate the reconsidering of software at every device. CONSTITUTION:A matrix circuit 1 outputs count preset values 111 set in accordance with a CPU specification signal 100, a CPU operating frequency signal 101, and a bus operating frequency signal 102 to a counter circuit 2. The counter circuit 2 subtracts the count preset value 111 from the matrix circuit 1 from a counter start-up signal 151 representing the detection of an I/O instruction provided with a specific I/O address from a CPU 4 by a decoder circuit 5 when it is inputted. A wait control circuit 3 requests waiting to the CPU 4 by activating a ready signal 131 when the counter startup signal 151 from the decoder circuit 5 is inputted, and cancels such wait request for the CPU 4 by activating the ready signal 131 when a count-out signal 121 is inputted from the counter circuit 2. |
