| 摘要 |
<p>A dynamic random access memory (DRAM) device comprising: a plurality of sense amplifiers [SA]; bit lines [BL] connected to the amplifiers, respectively; a first group [F] of memory cells [MC] arranged in a row and connected to one of the bit lines; and a second ground[S] of memory cells arranged in a row and connected to the same bit line; the first and second groups being arranged side by side and adjacently to each other, shifted one from the other by a half of a memory cell pitch, and connected alternately to each other in an open bit line system.</p> |
