| 摘要 |
This mediator allows a mediation in a short time regardless of the number of request signals through mediator modules with a specific logical circuit. This is composed of: a request signal generator which generates request signal to the mediation module; an acknowledgement signal generator which generates acknowledgement signals; a trigger signal generator which generates trigger and prohibition signals through request and acknowledgement signals; a delay which delays the process as long as the trigger generating time and remembers the priorioty; an RS latch which is composed of AND gate; and an input logical circuit which operates the RS latch.
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