| 摘要 |
<p>A data processing system (10) has more general purpose physical registers than architectural (logical) registers. The system (10) uses a logical register content-addressable memory (LRCAM) (40) to map logical registers to physical registers, and to monitor the assignment of physical registers. Each physical register (48) has a CAM cell (50) associated with it. The CAM cell (50) stores the logical register number mapped to that physical register (48), and a flag bit for indicating whether the physical register (48) is currently assigned to a logical register. As a sequencer (20) issues instructions, source logical registers are translated to physical register by applying the logical register number to all CAM cells, and directly selecting the matching physical register. After the LRCAM (40) translates the source registers, the destination logical registers to be written are mapped to physical registers allocated from a free pool of registers, while the LRCAM (40) simultaneously unmaps physical registers formerly assigned to these destination logical registers. <IMAGE></p> |
