CONVERTER FOR INTERCONNECTING AN ASYNCHRONOUS TELECOMMUNICATION NETWORK AND A SYNCHRONOUS NETWORK

摘要

The converter comprises a memory (SRAM) having first and second ports, a first port management circuit (SPM) connected to the first port, to an incoming synchronous multiplex line (ME) and to an outgoing synchronous multiples line (MS), and a second port management circuit (APM) connected to the second port, to an incoming asynchronous link (LE) via an FIFO type packet memory (M) and to an outgoing asynchronous link (LS). An external command (MF) applied to the port management circuits selects the converter operating mode; in a first mode (M32) each time slot of a frame of a synchronous multiplexed signal is assigned to one communication channel and in a second mode (M1) all the time slots of a synchronous frame are assigned to one channel.