| 摘要 |
The tester circuit tests hardware and software of a system which has CPU with ease. The tester includes an address decoder (40) for decoding address signal transmitted from a CPU (10), a latch (50) for generating a first and a second signal according to output signal of the address decoder (40) and data signal transmitted from a CPU (10), a pulse generator (70), a pulse generator (70) for generating pulse signal synchronized to CPU operation when a first signal is received, a pulse counter (60) for counting operating steps of a CPU (10) when a third mode signal is received, and a multistep driver (100) for generating and transmitting a first and a third mode signal to operate a CPU (10) step by step.
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