发明名称 SEMICONDUCTOR MEMORY RETAINING CIRCUIT
摘要 PURPOSE:To compensate the end effect of a semiconductor memory in a device for arraying memory cells by dispersely disposing the dummy cells at the respective lines of the array and increasing the branch current of the dummy cell disposed at the end. CONSTITUTION:Dummy cells Ced1, Ced2 associated with a circuit for branching a writing current of a memory cell and a retaining current supplying circuit in a semiconductor integrated circuit disposed with the memory cells in array are dispersely disposed in the respective lines of the array. Retaining current supplying transistor Q7a is also provided in the each of the dummy cells. The injector area of the transistor Q7e is increased in the dummy cell used at the end to compensate the end effect by flowing sufficient current thereat.
申请公布号 JPS55163872(A) 申请公布日期 1980.12.20
申请号 JP19790071119 申请日期 1979.06.08
申请人 FUJITSU LTD 发明人 TOYODA KAZUHIRO;OONO SATOSHI
分类号 H01L27/082;H01L21/8226;H01L21/8247;H01L27/102;H01L29/788;H01L29/792;H03K19/091 主分类号 H01L27/082
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