| 摘要 |
PURPOSE:To degrade respective entry units of a cache memory without increasing the quantity of hardware by making the effective bit of an entry corresponding to a cache memory directory part ineffective when an error occurs to a cache memory data part. CONSTITUTION:For a read to cache memory data part 14, a read address is set in an address holding circuit 11, a cache memory directory part 13 is looked up with the low-order address signal 112 of the address, and an address signal 131 and effective bit signal 132 of the corresponding entry are sent out. A comparing circuit 15 compares the high-order address signal 111 sent out of the address holding circuit 11 with the address signal 131 sent out of the cache directory part 13 and sends a coincidence signal 151 out when they match each other. If the data read out of the cache memory data part 14 has an error, the effective bit of the directory part 13 corresponding to the entry having the error is made ineffective. |
