发明名称 CHECK POINT SYNCHRONIZATION ENABLING PARALLEL PROCESSING OF INSTRUCTION
摘要 PURPOSE: To attain the processing of a check point function instruction and the processing of an instruction except the check point instruction in parallel by setting a check point just before and just after the check point function instruction. CONSTITUTION: A data cache 210 includes a storing operation queue 210A, data cache memory array 210B, and check point controlling part 210C. The storing operation queue 210A is a queue for holding an address and control information for an operand storing operation buffered in storage to be buffers 232A-232C. The data cache memory array 210B is a cache memory related with the set operation of a general constitution. Also, the check point(CKPT) controlling part 210C of the data cache 210 executes an operation for judging the end of CKPT synchronization when the CKPT synchronization ends. Then, a CKPT is set just before and just after a CKPT function instruction.
申请公布号 JPH05210526(A) 申请公布日期 1993.08.20
申请号 JP19920202291 申请日期 1992.07.29
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 SUTEIIBUN TAIRAA KONFUOOTO;KURIFUOODO OOEN HAIDEN;JIYON SUTEIIBUN RIPUTEI;SUUZAN BAABARA SUTEIRUMAN;CHIYAARUZU FURANKURIN UEBU
分类号 G06F9/38;G06F11/14 主分类号 G06F9/38
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