发明名称 SCAN-PATH CIRCUIT
摘要 PURPOSE:To greatly shorten the time from the interruption to the restart of an error processing by making the number of shift clocks, required to scan all scan paths, much less than that in a case wherein the scan paths can be put in operation only individually. CONSTITUTION:Scan-path circuits SP1 and SP2 wherein the number of registers is (i), the number of scan clocks is (j), and the remainder obtained by dividing (j) by (i) is (k) are equipped with a means which selects one of the output of the register at the head of the scan path and scanned-in data as the scan input to the register at the tail of the scan path when k=0, a means which uses the output of the head register of the scan path as the scan input to the tail register of the scan path when knot equal to 0, and a means which selects one of the scan output and scanned-in data of a (k+1)th register as the scan input to a (k)th register.
申请公布号 JPH05210532(A) 申请公布日期 1993.08.20
申请号 JP19910329292 申请日期 1991.12.13
申请人 NEC CORP 发明人 NOBUTAKA YASUSHI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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