| 摘要 |
PURPOSE:To shorten the hunting time for frame synchronization recovery by providing delay circuit composed of RAM, as many as frames, in one multi-frame. CONSTITUTION:When a string of received digital codes of fixed frame constitution is supplied to terminal 301 and a clock is input from terminal 302, timing generating circuit 303 generates signals of read and write phase W/R and read timing CLK, and address counting circuit 304 generates repetitive addresses as many as bits constituting one frame. At this time, frame-synchronizing pulses appear at the outputs of delay circuits 310-321 using RAM at every time of a fixed number of bits, and are detected by a pattern detecting circuit composed of NAND gate 330, and inverters 340-345 before being output. Circuit 304 divides clock pulses, synchronizing with a string of received digital codes, at a dividing ratio determined by the frame constitution to generate an address signal, and consequently delay circuits are sequentially shifted, so that when a frame-synchronizing pulse appears at the same address of each delay circuit, it will be dtected and output. |
