发明名称 |
HARDWARE EMULATION ACCELERATOR AND METHOD |
摘要 |
A simulation system for a microelectronic device having two or more functional modules from a megacell library, the simulation system utilizing actual physically implemented versions of each functional module (or block) from the megacell library so as to provide a more accurate and much faster simulation than a comparable software- or field programmable gate array-based simulation. The simulation system comprises means for providing a physically-based implementation of each functional module of a proposed design for a microelectronic device, the physically-based implementation being disposed on one or more test microelectronic devices used by the simulation system. Interconnecting means is used for electrically coupling together each of the physically-based implemented functional modules so as to produce the proposed design of the proposed microelectronic device. Emulation is performed by applying one or more test vectors at a preselected clock speed of the proposed design using the physically-based functional modules electrically coupled together to produce the proposed design, wherein the test vectors can be completed much faster as compared to a comparable software- or field programmable gate array-based simulation and wherein the results of the test vectors are much more accurate than the comparable simulations because the physically-based functional modules are used at a comparably lower cost. |
申请公布号 |
WO9316433(A1) |
申请公布日期 |
1993.08.19 |
申请号 |
WO1993JP00149 |
申请日期 |
1993.02.05 |
申请人 |
SEIKO EPSON CORPORATION |
发明人 |
LIN, CHONG, MING;NGUYEN, LE, TRONG;HO, WAI-YAN |
分类号 |
G01R31/28;G06F11/26;G06F17/50 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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