| 摘要 |
PURPOSE:To reduce the jitter of a VCO clock and to improve the reliability of data read-out by generating a signal having a pulse width exceeding the pulse width within which a charger pump can respond and avoiding a non- sensible band at stable time. CONSTITUTION:Each time a read-out signal 11 is inputted, a charge or discharge signal is outputted to a charger pump for a certain period of time. Under this state, being stabilized, the system controls a phase error signal so that a same amount of operation having inverted polarity can be made with respect to charging or discharging which is performed normally. That is, the phase error signal is equivalent to the pulse width of a charge or discharge signal for the certain period of time to be outputted to the charger pump 3. Thus, by setting the pulse width to minimum time or more within which current switches 29 and 30 of the charger pump 3 can respond, the closed-loop state of the system at the stable time can be avoided. |
