发明名称 PN PATTERN ERROR DETECTING CIRCUIT
摘要 <p>PURPOSE:To reduce the numbers of wiring wires and gates by directly giving data from an evaluation object to a PN pattern generating circuit. CONSTITUTION:When an PN pattern (e) generated by the PN pattern generating circuit 40 and output data (b) of the evaluation object are coincident, the output of an Ex-NOR gate 51 comes into a level H, which expresses being normal. On the contrary, both inputs are dissident, the gate 51 comes into a level L and it becomes an alarm (d). On the other hand, even if D-flip-flops constituting the circuit 40 all come into a reset state, data (b) from the evaluation object is inputted so that the reset state of all D-flip-flops does not loop and the system is automatically started from the point where data (b) comes into the level H. Thus, an AND gate and an OR gate which are conventionally necessary become unnecessary so that a circuit scale can be reduced, wiring errors are reduced and the yield is improved.</p>
申请公布号 JPH05206991(A) 申请公布日期 1993.08.13
申请号 JP19920011332 申请日期 1992.01.24
申请人 FUJITSU LTD 发明人 IKEDA YOSHINAO
分类号 H04L1/00;H04L7/00 主分类号 H04L1/00
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