发明名称 PACKET SWITCHING SYSTEM
摘要 <p>PURPOSE:To reduce delay to maintain the sequence of a packet in a multistage connection packet switching network. CONSTITUTION:A device 101 which finds reference time finds the minimum value of time stamp of the packets located at the leading positions of FIFO input buffers 103, 104, and sets them as the reference time at this stage. An effective packet provided with the minimum time stamp is selected, and it is accumulated in FIFO output buffers 105, 106 at desired output terminals via a time division multiplex bus 102. However, such operation is performed for N times at certain packetizing time at an input/output terminal. When the packet is outputted from the FIFO output buffer, an idle packet is outputted to the next stage by attaching the reference time when the buffer is vacant. When the packet located at the end position in the buffer is the effective packet, an inputted packet is written on the FIFO input buffer behind the packet, and when the last packet is the idle packet, the inputted packet is written on it.</p>
申请公布号 JPH05207062(A) 申请公布日期 1993.08.13
申请号 JP19920011544 申请日期 1992.01.27
申请人 NEC CORP 发明人 HAN ZUISETSU
分类号 H04L12/56;H04Q11/04 主分类号 H04L12/56
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