发明名称 MULTIPLIER
摘要 PURPOSE:To suppress the expansion of circuit size to its minimum and to attain a prescribed multiplying function in a digital multiplier without increasing the number of input bits even if an input value variable area is expanded. CONSTITUTION:A selector 14 for selecting either one of an original output bit and an output bit lower than the original one only by one bit is arranged on the post stage of a multiplying operation part 10 in a multiplier of 6 bits *6 bits. When inputs 111 to 116 are 0 to 63, the selector 14 selects the original bit. When 32 is inputted to the input 111 to 116 and the selector 14 selects the lower output bit, a result multiplied by 64 is obtained.
申请公布号 JPH05204607(A) 申请公布日期 1993.08.13
申请号 JP19920014617 申请日期 1992.01.30
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HARA YOSHIHIRO
分类号 G06F7/00;G06F7/52;G06F7/523;G06F7/53 主分类号 G06F7/00
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