LOGIC CIRCUIT USING VERTICAL-TYPE STACKED HETEROJUNCTION FIELD-EFFECT TRANSISTOR

摘要

PURPOSE: To provide a logic circuit using a hetero-bonding field effect transistor structure having a vertical lamination complimentary device. CONSTITUTION: A P-channel quantum well 12 and an N-channel quantum well 14 are formed closely to each other under a gate electrode 17 and separated each other by a thin film barrier material 13. P-source and P-drain region 18 are bonded to the P-channel. N-source and N-drain region 19 are bonded to the N-channel. As P-source/drain region 18 is insulated from the N-source/drain region 19, P-channel device and N-channel device are connected to each other, and various logic function are provided.