| 摘要 |
PURPOSE:To provide a printed wiring board where a wiring pattern is partially micronized in width without inducing impedance matching failure. CONSTITUTION:A multilayer printed wiring board 1 is provided, where an impurity injected layer 7 is provided to a region of an outer board 2a where an outer layer wiring 4g is partially narrowed in width, and the region of the outer board 2a is set larger in dielectric constant than the other region. In the multilayer printed wiring board 1, as the region where the outer layer wiring 4g is narrowed in width is enhanced in inter-wiring layer capacitance, the increase of the region concerned in reactance caused by that the outer layer wiring 4g is partially narrowed in width is offset, and in result the outer wiring 4g can be kept constant in specific impedance. |
