发明名称 SERIAL BIT EXTRACTION CIRCUIT
摘要 <p>PURPOSE:To provide the excellent serial bit extraction circuit of a small circuit scale by generating plural extraction clock signals to extract the prescribed bit of the different kinds of the frames of a multiframe by a single counting means. CONSTITUTION:Plural data extracting means 1, 4 to extract the prescribed bit from each time slot of time division multiplexed serial data in response to the extraction clock signal, and the single counting means 3 to generate plural extraction clock signals to be supplied to each of plural data extracting means from a frame pulse synchronized with the frame of the serial data and a clock pulse synchronized with the bit of the serial data, and data output means 6 to 8, 11 to 13 to output bit data obtained from the data extracting means 1, 4 as all the bit data of the time slot of '1' are provided.</p>
申请公布号 JPH05207004(A) 申请公布日期 1993.08.13
申请号 JP19920023372 申请日期 1992.01.14
申请人 HITACHI TELECOM TECHNOL LTD 发明人 WATANABE YOSHIMI;OTA YUKINORI;ATSUMI EISUKE
分类号 G06F15/00;H04L7/08;H04N5/08 主分类号 G06F15/00
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