| 摘要 |
A circuit arrangement of a semiconductor integrated circuit device includes logic cell arrays (12, 13, 62, 63) arranged into columns. Each of the logic cell arrays have a plurality of logic cells (14). Each of the logic cells have at least one monitor point (15). The circuit arrangement also includes select lines (16, 65) which carry select signals, each specifying a corresponding one of the logic cell arrays. Further, the circuit arrangement includes read lines (17, 64) carrying monitor signals showing logic states of monitor points of the logic cells, the select lines and the read lines being provided so that the total number of the select lines and read lines is less than the sum total of the number of the logic cell arrays and a maximum number of monitor points contained in one of the logic cell arrays, and switch elements (18) connecting the monitor points of the logic cells to the read lines in response to the select signals. |
