| 摘要 |
The image processor includes a main processor, a controller and a frame memory to store image data. It also has a source counter, a convolution processor, an adder, a data latch circuit, a pipeline register, a bus buffer, a buffer RAM, an address counter, an address register and a destination counter. A frame memory stores the result. A convolution operation with coefficient matrix data on each pixel of the frame memory is carried out by storing the result of an intermediate operation in the buffer RAM. This result is then added to the result of the next intermediate operation successively. |
