| 摘要 |
<p>PURPOSE:To attain simultaneous access from plural devices by forming a memory circuit read and outputted from the i-th (i=1-n) line while storing write data from the 1st address line. CONSTITUTION:When address information for read is transmitted from a display controller onto an address line 19 during write access from a CPU, a row decoder 21 and a column decoder 23 make a row selecting signal line 12i (i=2) and a column selecting signal line 14j(j=1) significant respectively. Then, a memory cell 10ij(i=2, j=1) is possible for read regardless of write accessing state. Through the constitution above, the write/read access from the CPU and read access from the display controller are attained asynchronously and simultaneous access is attained also.</p> |
