| 摘要 |
<p>PURPOSE: To reduce the number of refreshing executions, while preventing the sensing merge deterioration of a bit line by reducing the number of times of refreshing executions at the time of a data possessing mode and improving a word line boosting level. CONSTITUTION: When a self-refreshing signalϕself is high and a mode is the data possessing mode, a refresh cycle control means 1 outputs an output L to the highest-order bit of a row address, a highest-order bit line becomes don't- care state, a bit line with respect to a bit next to the highest-order bit is successively enabled, and the number of refreshing times is reduced to 1/2. At the same time, a boost signal from a word line boosting level generation part 2 is improved to prevent the deterioration of the sensing margin of a bit line caused by the increase of the number of refreshing memories, with the reduction of the number of refreshing executing times.</p> |
