发明名称 SYNCHRONOUS MULTIPLEXER
摘要 PURPOSE:To reduce circuit scale and to simplify control by terminating a B3 byte detector in the front step of a time switch part and inserting it to a G1 byte immediately when far end block error (FB) information is generated. CONSTITUTION:A path overhead(PO) terminating part 101 is installed in the front step of a time switch part 111 and plays a role for terminating PO contained in an input STS-1 signal 104. Each PO is terminated by a PO terminating part 102, a B3 byte it the PO is compared with the parity of the data sequence of the input STS-1 signal 104, and the error of a path is recognized. FB error is generated with the purpose of being returned as FB information by an FB generator 105, and the FB is inserted to the FB part of a G1 byte part by a G1 byte FB inserter 106. Next, the STS-1 signal is inputted to the switch part 11 and cross connected. Afterwards, the STS-1 signal is transmitted to a PO inserting part 121, each PO excluding the FE information is inserted by an inserting part 122, and an STS-1 signal 123 is outputted.
申请公布号 JPH05199201(A) 申请公布日期 1993.08.06
申请号 JP19920009443 申请日期 1992.01.22
申请人 NEC CORP 发明人 SHIMADA NAOHIRO
分类号 H04J3/06;H04J3/00;H04J3/14;H04J3/16;H04Q11/04 主分类号 H04J3/06
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