| 摘要 |
PURPOSE:To offer a circuit with ease of timing design and high general-purpose application and expansion by providing a logical gate circuit combining >=one output of an FF circuit constituting a ring counter and giving an output. CONSTITUTION:In figure (a), outputs Q20, Q22, Q23, Q24 of the ring counter are inputted to an exclusive OR circuit 15. Thus, an output TX2 of the circuit 15 is changed at a change in each output to obtain a timing signal T2 with plural changes within one period. Outputs Q30, Q32, Q33 are inputted to an exclusive OR circuit 17 as shown in figure (b) to obtain a timing signal inverted at odd and even number periods as a timing signal T3.
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