| 摘要 |
PURPOSE:To attain a carry circuit with a small number of gates by having combinations with high efficiency among the sum logical gates having the input/ output separating function and the product logical gates having no input/output separating function. CONSTITUTION:A basic cell is formed with 6 gates, an addition signal generating circuit, two sum logical gates and a product logical gate which uses the output signal of said sum logical gates as input signals. While an adder is obtained with combinations of such basic cells. A half addition sum signal FN=AN+BN(FN +CN-1).(AN+BN) emerges on an output line 20; while a signal [-FN +(-CN-1)].[-AN+(-BN)] emerges on an output line 22. The signal (-FN+ CN-1).(AN+BN) is set at logic '1' only when >=2 inputs are equal to logic '1' among three input signals AN, BN and CN-1. While the signal [-FN +(-CN-1)].[-AN+(-BN)] is set at logic '1' only when <=2 inputs are equal to logic '1' among said three signals. Thus a carry signal CN to be applied to a desired high-order bit is obtained together with the corresponding NOT signal -CN. |
