MEANS TO AVOID DATA DISTORSION IN CLOCK-SYNCHRONIZED SIGNAL SAMPLING

摘要

Signal-sampling apparatus wherein information signals are directed to a register (24) under the control of first clock pulses (CLK 1) and are latched into the register under the control of second clock pulses (CLK 2). A calibrator (40) monitors the timing of the first and second clock pulses to determine if they are so close together that data signals subsequently output from the register will be distorted so as to cause errors in downstream devices. If such condition is found, the calibrator (40) inverts the phase of the second clock pulses (CLK 2) to assure proper time spacing to avoid data corruption.