| 摘要 |
The gate resistance and inductance of power transistors, such as MOSFETS, on a chip are substantially reduced and evenly distributed among the individual MOSFET cells of the chip. The gate terminal of a power MOSFET includes a plurality of gate pads coupled to each other by a gate runner (26) along the periphery of the chip; the number and locations of the gate pads (22) depending on predetermined values of gate resistance, gate inductance, and on-state resistance of the MOSFET, As a result, resistive and inductive losses are reduced; gating of the individual MOSFET cells is substantially synchronized; and device gain is improved. Hence, device efficiency is improved by reducing the time required to reach the minimum on-state resistance thereof. The invention also applies to the base pads of bipolar transistors. <IMAGE> |
