Semiconductor memory device incorporating redundancy memory cells having parallel test function.

摘要

In a semiconductor memory device which can perform a parallel test upon a predetermined number of memory cells by using a degenerate address (X0-X9, Y3-Y10) of a plurality of first addresses each corresponding to one memory cell, when a defective memory cell is found by a parallel test using the degenerate address, an address whose space includes the space of the degenerate address is written into only one location of its corresponding redundancy decoder to replace the defective memory cell with its corresponding redundancy memory cell.