发明名称 |
Packet switch suitable for integrated circuit implementation |
摘要 |
A packet switch for high-speed synchronous multiplexing of voice and picture communications collectively. The packet switch uses among other things an input multiplexer, and output demultiplexer, and a single buffer memory divided into memory areas connected to multiple input and output lines. The subdivided buffer is controlled by counters rather than a more complicated address exchanger. A second embodiment eliminates the need for an output demultiplexer because of individual read/write control of the buffer units. A third embodiment includes a bidirectional bus between an input buffer and an output buffer. A fourth embodiment uses a more economical unidirectional bus. The unidirectional bus can be limited to a part of an input packet to permit Large Scale Integration (LSI). In the LSI configuration, address filters may be replaced with a centralized address controller, and the buffer can consist of FiFo memory units or RAM units.
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申请公布号 |
US5233603(A) |
申请公布日期 |
1993.08.03 |
申请号 |
US19910771865 |
申请日期 |
1991.10.08 |
申请人 |
NEC CORPORATION |
发明人 |
TAKEUCHI, TAKAO;SUZUKI, HIROSHI;IWASAKI, SUSUMU;NAGANO, HIROSHI;SUZUKI, TOSHIO |
分类号 |
H04L12/56 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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