| 摘要 |
In a digital summing process that sums non-linear digital signals by converting them to linear signals, computing their two's complement, summing the two's complements together and converting the resultant into a non-linear resultant, the fidelity of the summing process may be verified in the following manner. When only one non-linear digital signal is being summed, an algorithm determines whether the one non-linear digital signal being summed is equivalent to a predetermined value which, when passed through the summing process, will yield a different value than the one inputted. If the algorithm determines that the one non-linear digital signal is equivalent to a predetermined value, it sets a flag which indicates that the resultant over written with the predetermined value. Once the resultant is overwritten with the predetermined value, the flag is reset.
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