发明名称 |
COMPUTER VIDEO GRAPHIC SYSTEM |
摘要 |
<p>PURPOSE: To provide a video system having plural programmable operation modes and a refresh buffer. CONSTITUTION: A pack level detecting circuit 202 recognize a time when the pack level of a first-in first-out buffer(FIFO) 201 reaches a previously fixed level being specifiedly 3, 5 or 6 double words or the level more than that. A central processing unit can write new video data in a video memory 113 by a processor access circuit. Whenever the present pack level is equal to below a min. pack level which is set by a pack level selecting circuit 205, the processing unit access circuit is in a disenable state. The central processing unit performs access to the video memory 113 only when min. level data exists in FIFO 201, and the min. level data is selected in accordance with a present operation mode.</p> |
申请公布号 |
JPH05188892(A) |
申请公布日期 |
1993.07.30 |
申请号 |
JP19920143397 |
申请日期 |
1992.05.09 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
SUTEFUAN PATORITSUKU TONPUSON |
分类号 |
G06F3/153;G06F3/14;G06F5/06;G06F5/10;G06F5/12;G09G1/16;G09G5/00;G09G5/36;G09G5/393;G09G5/395 |
主分类号 |
G06F3/153 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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